Cover Letter

I-Shuan Tsung
istsung@gmail.com
Date: 2009/06/03

To Whom It May Concern,


My name is I-Shuan Tsung. I'm looking for full-time employment to continue strong hardware system and design skills in design, validation or verification related capacity.

After graduated from NCTU Taiwan, I knew that I have great interests in computer architecture and design field; hence I perused a MSEE in the Department of Electrical and Computer Engineering at the University of Texas at Austin. I followed Dr. Yale Patt in his Microarchitecture and Computer Architecture courses which provided me strong groundwork in computer architecture and design field. The most valuable content I learned from Dr.Patt was his methods of thinking and problem solving. It is a method enables me to conduct research in related fields, identify the goal, find out the missing piece, and propose and implement a solution. Later on I followed Dr. Earl Swartzlander doing research on floating-point computer architecture and design which forms the basis to my future work - graphic unit architecture and design.

During the internship in Advanced Micro Devices (AMD), I participated in a group designs and optimizes floating-point arithmetic unit for a graphic processing unit. I gained valuable industrial experiences on design R&D work and team work. I learned procedures of R&D project, aspects that should be emphasized, and problem solving methods. I am also practically aware the importance of critical thinking and communication skills. The most impressive experience during my internship is the brainstorming meeting in which R&D team members and university professors joined together and discuss about directions of future product, implementations of theory and academy value of the team's research results. I witnessed how innovation is implemented. It has a great impact on me. These internship experiences have made me more determined that ASIC design and related fields are the direction I plan to dig into as a career.

I am working as a contract IC architecture engineer for graphic unit vector floating-point core in Institute for Information Industry, Taipei, Taiwan. I am responsible for designing instruction set architecture for the pipeline arithmetic shader core in this graphic processing unit. This project is targeted to make a prototype product from research results of National Taiwan University for Taiwan graphic processing hardware industry. In this project, I am responsible to design a vector floating-point instruction set architecture from scratch. I am also responsible to design the floating-point pipeline processing core for this ISA. Then, I simulated it with Verilog RTL. The final goal is to implement this design on an FPGA board. This project gave me a chance to prove to myself that I am able to design hardware architecture from scratch. I practiced most of the design techniques during this project. I also use this opportunity to build up a design routine for myself and many working efficient routines for tools that I need to use daily. I took this working experience as a proof to myself that I am able to work independently and as a team member and also am able to apply knowledge that I have learned from school on practical work.

I have professional knowledge and skills of ASIC design and am willing to learn and work as a team. I have practical experiences of IC design from the industry and am very interested in works related to it. I understand the importance of communication and team work. I have confidence to myself that I can contribute to your prestige company. I hope that I could have a chance to contribute my professional skills to your prestige company.


Sincerely,

I-Shuan Tsung

English Resume

I-Shuan Tsung
Email: istsung@gmail.com
Website: http://istsung.blogspot.com/


Objective

I'm currently working as a verification engineer in Apple Inc.. I'm not interested in switching jobs right now.


Education

M.S. Electrical and Computer Engineering, Computer Engineering Track,
Graduate Date: Fall 2007
The University of Texas at Austin 3.4/4.0
B.S. in Computer Science and Information Engineering,
Graduate Date: Jun 2004
National Chiao-Tung University, HsinChu, Taiwan 3.4/4.0


Relevant Courses

Floating-point Computer Arithmetic and Design, High Speed Computer Arithmetic and Design (E. Swartzlander), System-on-chip Design, Microarchitecture (Y. Patt), Superscalar Miroarchitecture, Computer Architecture (Y. Patt), Analyze and Design Digital Integrated Circuit, Assembly Language, Logic Design, Computer Organization, Microelectronics, Data Structure.


Professional Experience

Industry

Apple Inc. Cupertino CA, Mobile Silicon Group, Verification Engineer 10/2009 -

Institution for Information Industry Taipei Taiwan, Contract RTL Design Engineer 03/2009 -
Graphic processing unit shader core ISA specification design, RTL design, simulation, synthesis.
Design shader core hardware for OpenGLES 2.0 SL.
Advanced Micro Devices Austin TX USA, Co-op Engineer 01/2008 - 05/2008
Graphic processing unit floating-point arithmetic unit microcode documentation and analysis.
Advanced Micro Devices Austin TX USA, Co-op Engineer 08/2007-12/2007
Develop automatic board testing user interactive program using C# and Visual Studio 2005.
Advanced Micro Devices Austin TX USA, Co-op Engineer 01/2007-05/2007
GUI implementation using C# and Visual Studio 2005.


Curricular

Floating-point addition unit simulation using Verilog, Floating-point Arithmetic and Design
Responsible for designing pipeline FP adder architecture and work assignments for the team.
Direct experience in designing and simulating short pass FP adder in Verilog.
Direct experience in project integration, verification and testing on Synopsys VCS.
IA-32 microprocessor design and implementation in Verilog, Microarchitecture
Participate in team effort to design and implement an Intel IA-32 microprocessor at gate level.
Responsible for designing and implementing the backend pipeline including memory access, execution, write back stages.
Direct experience in project integration, verification and testing on Synopsys VCS.
Microprocessor design and simulation in C, Computer Architecture
Design and simulate a microprocessor native in LC-3b ISA using C including virtual memory, exception and interrupt, unaligned access, and pipelining.
Integer multiplier simulation using Verilog, Computer Arithmetic and Design
Simulate and compare Wallace multiplier in Verilog. Verify and debug with Synopsys VCS.
DRM receiver hardware simulation using SystemC, System-on-chip Design
Design the receiver architecture and divide it into parts for team work.
Combine all parts and verify on SystemC platform.
An Evaluation of Optimization Algorithm for Mini-JIT Compiler, Senior Project
Evaluate folding algorithm performance on an x86 native environment.
Analyze and simulate Folding optimization algorithm embedded in Mini-JIT in C.
Design and simulate MIPS microprocessor in Verilog, Computer Organization


Skills

* Programming Language: Verilog, perl, C, C++, Java, x86 assembly, HTML
* CAD Tool: NCVerilog, Synopsis VCS, Verdi, Design Compiler
* OS: Linux, Unix, Windows, OS X
* Other Tool: MS Office
* Fluent in English and Chinese


Accomplishments

* Toastmaster International 04/2009 -
*President, National Chiao Tung University Photo Club 09/2001-06/2002
*Chief Execution Officer, National Photography Summer Camp 07/2002
*Chief of Programme, Civil Engineering Summer Camp 07/2002
*Host and Artist, Photography Exhibition 04/2002
*Staff, National Chiao Tung University Anniversary Celebration Activities 04/2002
*Photography Division Chief, Meichu Athlete Games 07/2001-03/2002
*Host, NCTU Track Meet Photography Contest 11/2001
*Staff, National Photography Summer Camp 02/2000-07/2001
*Staff, Civil Engineering Summer Camp 07/2001
*Photography Division Chief, Leadership Education Camp 02/2001

UT Austin Diploma

NCTU Diploma

UT Austin Transcript