English Resume
I-Shuan Tsung
Email: istsung@gmail.com
Website: http://istsung.blogspot.com/
Objective
I'm currently working as a verification engineer in Apple Inc.. I'm not interested in switching jobs right now.
Education
M.S. Electrical and Computer Engineering, Computer Engineering Track,
Graduate Date: Fall 2007
The University of Texas at Austin 3.4/4.0
B.S. in Computer Science and Information Engineering,
Graduate Date: Jun 2004
National Chiao-Tung University, HsinChu, Taiwan 3.4/4.0
Relevant Courses
Floating-point Computer Arithmetic and Design, High Speed Computer Arithmetic and Design (E. Swartzlander), System-on-chip Design, Microarchitecture (Y. Patt), Superscalar Miroarchitecture, Computer Architecture (Y. Patt), Analyze and Design Digital Integrated Circuit, Assembly Language, Logic Design, Computer Organization, Microelectronics, Data Structure.
Professional Experience
Industry
Apple Inc. Cupertino CA, Mobile Silicon Group, Verification Engineer 10/2009 -
Institution for Information Industry Taipei Taiwan, Contract RTL Design Engineer 03/2009 -
Graphic processing unit shader core ISA specification design, RTL design, simulation, synthesis.
Design shader core hardware for OpenGLES 2.0 SL.
Advanced Micro Devices Austin TX USA, Co-op Engineer 01/2008 - 05/2008
Graphic processing unit floating-point arithmetic unit microcode documentation and analysis.
Advanced Micro Devices Austin TX USA, Co-op Engineer 08/2007-12/2007
Develop automatic board testing user interactive program using C# and Visual Studio 2005.
Advanced Micro Devices Austin TX USA, Co-op Engineer 01/2007-05/2007
GUI implementation using C# and Visual Studio 2005.
Curricular
Floating-point addition unit simulation using Verilog, Floating-point Arithmetic and Design
Responsible for designing pipeline FP adder architecture and work assignments for the team.
Direct experience in designing and simulating short pass FP adder in Verilog.
Direct experience in project integration, verification and testing on Synopsys VCS.
IA-32 microprocessor design and implementation in Verilog, Microarchitecture
Participate in team effort to design and implement an Intel IA-32 microprocessor at gate level.
Responsible for designing and implementing the backend pipeline including memory access, execution, write back stages.
Direct experience in project integration, verification and testing on Synopsys VCS.
Microprocessor design and simulation in C, Computer Architecture
Design and simulate a microprocessor native in LC-3b ISA using C including virtual memory, exception and interrupt, unaligned access, and pipelining.
Integer multiplier simulation using Verilog, Computer Arithmetic and Design
Simulate and compare Wallace multiplier in Verilog. Verify and debug with Synopsys VCS.
DRM receiver hardware simulation using SystemC, System-on-chip Design
Design the receiver architecture and divide it into parts for team work.
Combine all parts and verify on SystemC platform.
An Evaluation of Optimization Algorithm for Mini-JIT Compiler, Senior Project
Evaluate folding algorithm performance on an x86 native environment.
Analyze and simulate Folding optimization algorithm embedded in Mini-JIT in C.
Design and simulate MIPS microprocessor in Verilog, Computer Organization
Skills
* Programming Language: Verilog, perl, C, C++, Java, x86 assembly, HTML
* CAD Tool: NCVerilog, Synopsis VCS, Verdi, Design Compiler
* OS: Linux, Unix, Windows, OS X
* Other Tool: MS Office
* Fluent in English and Chinese
Accomplishments
* Toastmaster International 04/2009 -
*President, National Chiao Tung University Photo Club 09/2001-06/2002
*Chief Execution Officer, National Photography Summer Camp 07/2002
*Chief of Programme, Civil Engineering Summer Camp 07/2002
*Host and Artist, Photography Exhibition 04/2002
*Staff, National Chiao Tung University Anniversary Celebration Activities 04/2002
*Photography Division Chief, Meichu Athlete Games 07/2001-03/2002
*Host, NCTU Track Meet Photography Contest 11/2001
*Staff, National Photography Summer Camp 02/2000-07/2001
*Staff, Civil Engineering Summer Camp 07/2001
*Photography Division Chief, Leadership Education Camp 02/2001
